Hierarchy

The 2019 Nyquist Lecture in Electrical Engineering

"Hierarchy"

Dr. Ivan Sutherland
Asynchronous Research Center (ARC) at Portland State University

Bio: Ivan Sutherland is a long-time evangelist for self-timed systems. His 1988 Turing Award paper, Micropipelines, inspired interest in self-timing. He is a member of both the National Academy of Engineering and the National Academy of Sciences. He is sometimes called the "father of computer graphics" for his 1963 PhD work in that field, but now, more than half a century later, he prefers the nickname "God Father of Virtual Reality" received for building the first very crude head-mounted display in 1968. Now 80 years of age, rather than "not planning to retire," he "plans not to retire." Ivan and his research partner and wife, Marly Roncken, run the Asynchronous Research Center (ARC) at Portland State University.

Abstract: Integrated circuits have at least three separate hierarchies. First, a system designer breaks a design into a hierarchy of parts understandable by him. All too often the designer ignores wires in his hierarchy, thinking mainly of computation. Ignoring wires is a bad mistake because the wires in CMOS circuits consume most of the energy, cause most of the delay and occupy most of the area. We think of the design hierarchy as a directed graph composed of Links that store and communicate data and the Joints between them that compute.

Second, a layout person thinks of the same design as a hierarchy of parts. Layout tools encourage him to make parts with fixed geometry. The layout person places "terminals" for easy connection by wires. Perhaps the terminals lie in rows and columns. The geometry of those terminals suits the kind of wires or cables available to connect the parts at the higher level of topology.

Third, a test person adds "scan" to collect and report values from diverse places. Scan is often a shift register or "scan chain" that reaches into most of the chip. The layout person connects test points to the scan chain in a sequence chosen strictly for layout rather than for logical convenience.

What happens if these separate hierarchies fail to match? What if the boundaries of the designer's conceptual parts fail to match the boundaries of the layout parts? How should scan chains, placed for layout convenience, appear in schematic diagrams?

Obviously, we need topological comparison tools that can deal with such boundary discrepancies. But far worse, using layout topology at the conceptual level has led the asynchronous community to ignore wires and thereby go seriously astray.

Hosted by: Professor Rajit Manohar

Tuesday, April 16, 2019
Davies Auditorium- 4:00 PM