Building Defenses in Processors against Speculation Attacks

Time: Wednesday, February 24, 2021 - 3:45pm - 4:45pm
Type: Seminar Series
Presenter: Josep Torellas; University of Illinois, Urbana-Champaign

Department of Electrical Engineering Seminar Series

"Building Defenses in Processors against Speculation Attacks"

Josep Torellas
University of Illinois, Urbana-Champaign 

Over decades, processors have been optimized to deliver high performance by transparently executing instructions out of order and speculatively. Recently, it has become obvious that this approach opens up major security vulnerabilities. We are now at one of the most difficult conundrums that computer designers ever faced: do we deliver performance or security, and at what complexity cost?

In this talk, I will describe the lines of research that we are following to address this problem, in cooperation with Intel. Hardware-only solutions, such as InvisiSpec and Speculative Taint Tracking, are effective but add complexity. Software-only solutions such as InvarSpec are flexible but not as effective. A better design point is needed. Moreover, new speculation-based attacks such as Microarchitectural Reply Attacks have been introduced. Hence, we need new defenses, such as Jamais Vu, which disables instruction replays. The talk will present a picture of a dynamic field that we are only starting to understand.

Josep Torrellas is the Saburo Muroga Professor of Computer Science at UIUC. He is the Director of the Center for Programmable Extreme-Scale Computing, a Co-Leader of the Intel Strategic Research Alliance Center on Computer Security, and past Director of the Illinois-Intel Parallelism Center. He has served in the Board of Directors of the Computing Research Association (CRA), and has been a Council Member of CRA's Computing Community Consortium. He serves in the International Roadmap for Devices and Systems (IRDS), and is a member of the U.S. National Academies Board on Army Research and Development.

Torrellas' research interests are computer architectures and technologies for shared-memory multiprocessors, and parallel computing. He has contributed to thread-level speculation, cache coherence and synchronization designs, and energy-efficient multiprocessor architectures. He has worked extensively with industry developing experimental computers. He a Fellow of IEEE, ACM, and AAAS. He received the IEEE Computer Society Technical Achievement Award, the IEEE CS Harry H. Goode Memorial Award, and the UIUC Campus Award for Excellence in Graduate Student Mentoring. He has graduated 43 doctoral students, who are now leaders in academia and industry. He received a PhD from Stanford University.

You are invited to a scheduled Zoom meeting. Zoom is Yale's audio and visual conferencing platform.

Topic: EE Seminar Series: "Building Defenses in Processors against Speculation Attacks" by Prof. Josep Torrellas
Time: Feb 24, 2021 03:45 PM Eastern Time (US and Canada)

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Meeting ID: 957 3741 0962
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