Yiorgos Makris

Associate Adjunct Professor of Electrical Engineering
Room / Office: Dunham 517
Office Address:
10 Hillhouse Avenue
New Haven, CT 06511
Mailing Address:
P.O. Box 208284
New Haven, CT 06520
Phone: (203) 432-1203
Email: yiorgos.makris@yale.edu

Ph.D., University of California at San Diego


Applications of machine learning and statistical analysis in secure and robust integrated circuits, with particular emphasis in the analog/RF domain. Error detection and correction methods for modern microprocessors. Test and reliability of analog, digital and asynchronous circuits. Soft-error tolerant design. Novel computational modalities using emerging technologies.

Selected Awards & Honors:

  • Yale Engineering Sheffield Teaching Prize  (2006)
  • Yale University Junior Faculty Fellowship  (2005)
  • Paul Moore Award for Developing Course “Semiconductors, Computers and Communications”  (2003)
  • Stavros S. Niarchos Faculty Research Grant for project “Who-is-who in Hi-Tech in Greece”  (2003)
  • Paul Moore Award for Developing Course “Digital Systems Testing And Design for Testability”  (2001)
  • INTEL Corp. Recognition Award  (1996)
  • Honors Graduate, University of Patras  (1995)
  • UCSD School of Engineering Industrial Fellowship  (1995)

Selected Publications:

  • M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, Y. Makris, “Instruction-Level Impact Analysis of Low-Level Errors in a Modern Microprocessor Controller,” IEEE Transactions on Computers (TCOMP), 2010 (to appear)
  • Y. Jin, Y. Makris, “Hardware Trojans in Wireless Cryptographic Integrated Circuits,” IEEE Design & Test of Computers (D&T), vol. 27, no. 1, pp. 26-35, 2010
  • S. Almukhaizim, F. Shi, E. Love, Y. Makris, “Soft Error Tolerance and Mitigation in Asynchronous Burst Mode Circuits,” IEEE Transactions on Very Large Scale Integration (T.VLSI), vol. 17, no. 7, pp. 869-882, 2009
  • F. Shi, Y. Makris, “Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits,” IEEE Transactions on Computers (T.COMP), vol. 58, no. 3, pp. 394-408, 2009
  • H-G. D. Stratigopoulos, Y. Makris, “Error Moderation in Low-Cost Machine Learning-Based Analog/RF Testing,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), vol. 27, no. 2, pp. 339-351, 2008
  • H-G. D. Stratigopoulos, Y. Makris, “An Adaptive Checker for the Fully Differential Analog Code,” IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 6, pp. 1421-1429, 2006
  • H-G. D. Stratigopoulos, Y. Makris, “Concurrent Error Detection in Linear Analog Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), vol. 25, no. 5, pp. 878-891, 2006